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what is the throughput  of pipelining ? If it has  4-stage pipelining with 800,500,400 and 300 picoseconds stage delays.
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When pipeline becomes stable, for each cycle an new instruction will be processed. It means CPI=1

Cycle Time should be more or equal to the maximum stage delay so that each state gets enough time to be stable. here it is 800 pico seconds. By the way, register Delay is missing here so we can consider it negligible.

avg time for 1 instruction= 800x10^-12 secs

1 sec= 1/(800x10^-12)

=1.25 GIPS

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