A cpu has cache with block size 64B . the main memory has k- banks , each bank being C-byte wide. Consecutive C-byte chunks are mapped on consecutive banks with wraparound. All the K –banks can be accessed in parallel, but to accesses the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k-banks in parallel .Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns . the latency of one bank access is 80ns . if c=2 and k=24, then latency of retrieving a cache block starting at address zero from main memory is ?
