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Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is 10 ns. Also assume that the setup time for the JK

 inputs of the flip flops is negligible.


as described

the answer is 50MHz question is

Answer not should be 30(3 And Gate ) + 10 ( Synch Circuit) = 40 ns

1/40 ns= 25 Mhz ?

Why here they have taken it only for 1 And and 1 FF ?

Note;I will close it when get satisfactory answer.

asked in Digital Logic by Active (1.8k points)   | 56 views

10 ns for all FF to generate their output

10 ns for all And gate to generate their output.

Note:- that we have to consider initial input Ji and Ki as either 0 or 1 for i = 2 and 3. And the output generated at the end of 20 ns will act as input for FF for next Final Output to be generated.

So we need total 20ns.

and Freq as 50 MHz.


i m satisfy that FF will take 10 ns and this things happen in parallel , while for AND gate plz describe how it is in parallely ?

1 Answer

+1 vote

well your suggested answer might be true in case of Asynchronous counter but above question represent synchronous counter.

And since you asked for explanation I suggest you to go through a good book (like morris manno for digital chapter 6) OR

for short explanation of difference between between async and sync

for detailed explanation :

answered by (173 points)  

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