Here assuming both instruction and data being in the same cache , so miss can happen either in instruction fetch or data fetch..Data fetch/write from memory will occur in load / store instructions.
Let us find the number of extra (stall) cycles per clock cycle on a cache miss .
So number of extra cycles per instruction = (Miss in instruction fetch + Miss in data fetch/write) * Miss penalty
= (Cache miss rate + % of Load/Store instruction * cache miss rate) * Miss penalty
= (0.15 + 0.3 * 0.15) * 5
= 0.975
Hence number of cycles needed in cache miss = 1.1 + 0.975 = 2.075
Hence speedup = Execution time in cache miss / Execution time in ideal condition
= 2.075 / 1.1
= 1.89