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Consider a CPU that executes at a clock rate of 200MHZ(5ns per cycle)with a single level of cache .CPI execution (i.e) CPI with ideal memory is 1.1.Instruction mix are 50% arithmetic/logical ,30% load/store , 20% control instructions.Assume cache miss rate is 15%and a miss penalty of 5 cycles.The number of times CPU with ideal memory is faster when no miss occurs

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Here assuming both instruction and data being in the same cache , so miss can happen either in instruction fetch or data fetch..Data fetch/write from memory will occur in load / store instructions.

Let us find the number of extra (stall) cycles per clock cycle on a cache miss  . 

So number of extra cycles per instruction   =   (Miss in instruction fetch + Miss in data fetch/write) * Miss penalty

                                                               =   (Cache miss rate  +  % of Load/Store instruction * cache miss rate) * Miss penalty

                                                               =   (0.15  + 0.3 * 0.15)  *  5

                                                               =   0.975

Hence number of cycles needed in cache miss   =   1.1  + 0.975   =   2.075

Hence speedup                                       =   Execution time in cache miss / Execution time in ideal condition

                                                             =   2.075  /  1.1

                                                             =   1.89  

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1.89 speed up ...very nice question....

(Cache miss ratio(instruction fetch)+cache miss ratio* (data fetch intsr))* miss penalty+ideal cpi

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