A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Opearnd Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?
| Instruction | Meaning of instruction |
|---|
| $t_0: \text{MUL} \:\text{R}_2,\text{R}_0,\text{R}_1$ | $\text{R}_2 \gets \text{R}_0*\text{R}_1$ |
| $t_1: \text{DIV}\: \text{R}_5,\text{R}_3,\text{R}_4$ | $\text{R}_5 \gets \text{R}_3 / \text{R}_4$ |
| $t_2: \text{ADD}\: \text{R}_2,\text{R}_5,\text{R}_2$ | $\text{R}_2 \gets \text{R}_5 + \text{R}_2$ |
| $t_3: \text{SUB} \:\text{R}_5,\text{R}_2,\text{R}_6$ | $\text{R}_5 \gets \text{R}_2 - \text{R}_6$ |
(A) 13
(B) 15
(C) 17
(D) 19
