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A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and the main memory unit respectively.

When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?

  1. 2 nanoseconds
  2. 20 nanoseconds
  3. 22 nanoseconds
  4. 88 nanoseconds
asked in CO & Architecture by Veteran (87.2k points)  
edited by | 4.1k views
A block to access in L2 cache requires 20 nanoseconds, and 2 seconds to place in L1-cache.

The block size in L1 cache is 4 words and there are total 16 words, so total time is 4*(20+2) = 88.
your answer seems right out of a textbook,even though there are 16 words since we have the offset bits wont we get the correct 4words in the first try itself instead of four tries

I think read and write could be done parallelly. It should be done parallelly because there is no bus delay and there is no buffer in picture(It could be there in side memory but it is not mentioned explicitly). So I think answer should be 20 ns.

4 Answers

+39 votes
Best answer
Ideally the answer should be 20 ns as it is the time to transfer a block from L2 to L1 and this time only is asked in question. But there is confusion regarding access time of L2 as this means the time to read data from L2 till CPU but here we need the time till L1 only. So, I assume the following is what is meant by the question.

A block is transferred from L2 to L1. And L1 block size being 4 words (since L1 is requesting we need to consider L1 block size and not L2 block size) and data width being 4 bytes, it requires one L2 access (for read) and one L1 access (for store). So, time = 20+2 = 22 ns.
answered by Veteran (294k points)  
edited by
@arjun sir
everything is done through
PC MDR and MAR so ideally answer b 22ns.
ref : http://stackoverflow.com/questions/12630151/can-multiple-cores-simultaneously-read-the-same-ram-location
Anyone Please tag this question as BARC2017 .

Here in GO we dont have much questions in in this tag.
But i want to ask can we transfer partial memory block?Like l2 is of 16 words ,so can we transfer partial block also of 4 bytes?
@Rahul At any level of memory hierarchy, the requester decides the block size. So, you should not say 'partial block'. Rather it is different block sizes at different levels.

Sir in ques:- http://gateoverflow.in/35154/write-back-and-write-through

the sizes of L1 and Main memory are different but still we transferred data block in terms  of size of Main memory and not L1.

we transferred 16 word entire block from main memory to cache and not based on cache word.

and in http://gateoverflow.in/130202/co-memory-organization, entire 2 word block is transferred from l2 to l1 on miss and 4word block from memory to L2 in case of miss.So why in these two questions requester's size not coming into picture in case of miss?

I am not able to get the point that in these two above links we are transferring data based on word size of L2 cache and not L1.But in this question we are  transferring based on L1 size.

Please clear confusion here Sir

+1 vote
i think this question is wrongly designed , because we know that whole block is transferred , since l2 has 16 words block and l1 has 4 words block suppose a block is missed in l1 then how can we search a 4 words block among 16 words block . both are of unequal sized block , but even according to question if it is possible then then we need to transfer whole block from L2 to L1 but but we have only 4 words path so we require four times to check l1 for miss and 4 times to bring 4 words each time to L1

 

so , 4(20+2)=88 nanosec
answered by Loyal (4k points)  
edited by
'how can we search a 4 words block among 16 words block'

Searching can be done by comparnig the index/tag bits. When we access L1 cache we find a block based on index bits and then compare that block's tag bits. If it's a miss then we need to do the same comparison in L2 cache.
0 votes
This question statement and diagram depicts that it is based on parallel hierarchy means direct access to L1,L2 or main memory is possible in it.

Since L1 miss

20 ns is required to access L2 and reading a block of size 16B.Since L1 is requesting which has block size of 4 B .only 4B transfer to L1 from L2 is required which takes an access of L1 to store block in it.

Thus L2 access (reading a block) + L1 (storing a block since it is parallel hierarchy by default it will not be copied to L1)

thus 20ns + 2ns = 22ns

Ans C
answered by Active (1.7k points)  
–4 votes
A block to access in L2 cache requires 20 nanoseconds, and 2 seconds to place in L1-cache. The block size in L1 cache is 4 words and there are total 16 words, so total time is 4*(20+2) = 88.
answered by Boss (5.5k points)  
See when L1 access L2, it is L1 block size that is in use, not L2. Otherwise when L2 access main memory, a page frame is fetched? Also, when CPU access L1, only a word is taken from L1- not L1 block.
Sir,This comment is very useful.I need to ask one thing.

If we have different block size in L1 and L2.Say

L1= 1 word block size with Access Time=2ns and L2=4 word block size with access time as 4 ns.

Now when there is a miss in L1,we will goto L2 and search one entire block to look for one particular word as asked by L1  and then if it is found,it will be transferred to the L1 cache. So basically we accessed one complete L2 block with 4*2=8ns  but just to transfer it to L1,it is 1 word time as L1 block size is 1 word and i.e what is asked in the question
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