During a program execution out of 1000 memory references there are 250 and 120 misses in L1 (Level1) and L2(Level2) caches respectively. Hit times for L1 and L2 cache are 24 and 40 cycles respectively. If there are 2.5 memory references per instruction, how many average stall cycles per instruction? (Assume L2 to memory miss penalty is 250 cycles)?
a)50
b)100
c)150
d)200