GATE CSE 2003 | Question: 47

Question

Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays $\delta_1 = 2 ns$ and $\delta_2 = 4 ns$ as shown in the figure. Both XOR gates and all wires have zero delays. Assume that all gate inputs, outputs, and wires are stable at logic level $0$ at time $0$. If the following waveform is applied at input $A$, how many transition(s) (change of logic levels) occur(s) at $B$ during the interval from $0$ to $10$ ns?

• A. $1$
• B. $2$
• C. $3$
• D. $4$

Comments

Option D is correct

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@bikram sir , I have following doubt on best answer .

1. This status will same for two seconds more. So, at 5th sec o/p of second non-inverting buffer reach at i/p of second xor gate because of its delay of 4sec i.e 1.

5th sec                                 1xor1=0                                                  0xor1=1

Answer 1

ans will be D

A  0000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

A' 0000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111(2 sec delay)

A''11111111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

A'''0000000000000000000000000000000000000000000000000000000000001111111111111111111100000000000000000(4 sec delay)

B111111111110000000000000000000000000000000000000000000000000011111111111111111111000000000000000000

B is final out put where 4 changes in logic

so ans is 4

Answer 2

hope you can understand,