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A digital system has clock  generator that produces pulses at frequency of 80 MHz design circuit that provides clock with cycle time of 50 ns

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$2$ edge triggered T Flip Flops can be used to do it.
Given clock frequency $= 80 \ MHz$,
 
desired clock frequency $= \frac{1}{50 \times 10^{-9}} \ Hz = 20 \ MHz$,
 
so we have to divide given clock frequency by $4$ in order to achieve the desired clock frequency.
 
This can be done with the help of two edge triggered $T$ flip flops as follows:
 

 
I am using -ve edge triggered flip flops here.
 
$T$ input of both the flip flops is $1$.
 
Clock pulses from the given clock generator are passed to the first flip flop.
 
Output of first flip flop i.e. $Q1$ will change only on the -ve edges of given clock pulse, so it can be seen from the pulse plot that frequency of $Q1$ will be half of that of given clock pulse.
 
So $Q1$ will produce pulse of frequency $40 \ MHz$.
 
$Q1$ is being fed to the clock input of second flip flop.
 
And the output of second flip flop i.e. $Q2$ will change only on -ve edges of $Q1$,so the frequency of pulse produced by $Q2$ will be half of the pulse produces by $Q1$ and quarter of the pulse produced by the given clock generator.
 
Thus the frequency of the pulse produced by $Q2 = \frac{80}{4} = 20 \ MHz$.
 
Hence $Q2$ if used as a clock, will provide the clock cycle time of $50 \ ns$.
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T  =  $\frac{1}{80MHz}$  = 12.5 ns

Using D flip flop 4 state counter at the Clock of 80MHz will produce the output.

T = 4*12.5 = 50ns

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