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Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?

  1. $11, 00$
  2. $01, 10$
  3. $10, 01$
  4. $00, 11$
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Best answer
35 votes
35 votes

For a cross-coupled $R-S$ flip flop with two NAND gates $11$ is no change and $00$ is forbidden. $00$ is forbidden (not allowed but not indeterminate) because in this state both $Q$ and $Q'$ equals $1.$ Moreover, in this state if inputs are changed to $11,$ next state is indeterminate (meaning we cannot determine the output)- $Q$ can be $0$ and $Q'$ can be $1$ or $Q = 1$ and $Q' = 0.$ There is also a chance that outputs can oscillate here when the following happens:

  1. Inputs are set to $11$
  2. When both inputs of NAND gates are $1$ output is $0$
  3. Suppose NAND gate 1 becomes $0$ first. 
  4. This $0$ goes as input to NAND gate $2$. 
  5. By this time NAND gate $2$ produces its own output as $0$.
  6. Now, this $0$ goes as input to NAND gate $1$ which makes its output $1$.
  7. The $0$ input to NAND gate $2$ (from step $4$) now makes its output $1.$
  8. Whole cycle can repeat and output toggles between $1$ and $0.$

This is just a possibility and that is why question says "may oscillate."

The input sequence 00,11 (Option D) may oscillate.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch

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20 votes

For R-S flip flop with NAND gates (inputs are active low) $11$-no change  $00$-indeterminat. So, option (A) may make the system oscillate as "$00$" is the final input. In option (D), after "$00$" flipflop output may oscillate but after "$11$", it will be stabilized.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch

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7 votes
7 votes

" a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation "

Oscillation means output is going to change every time.

As, 2 NAND gates are there , other 2 might be AND gate.

Now, circuit diagram will be like this

A) Now, at first R is getting 1 , that corresponding NAND gate producing 0.

That 0 is input of another NAND gate,

So, NAND gate corresponding to S getting input as  1 NAND 0=1 (As shown in picture below)

Now, it's 1st output is 0 1

Next, 0 1 ouput is  giving input to R and S

So, AND gate of R is producing 0 AND 1=0

NAND gate of R is giving 0 NAND 1=1(See picture again)

Similarly , AND gate of S getting input 1AND 1=1

R value previously was 0 (We donot know, R will produce first or S will produce first, So, taking previous value of R)

for NAND gate it is getting 0 NAND 1=1

So, 2nd output here is 1 1

Similarly keep check 1 1 as input as next AND gates

it will produce 0 0

So, if we put 11 as first input, it will keep toggleing , producing 01--11--00--11--00-------------------

D) if we give 00 first in same circuit it will produce as output 00--11--11--11--11------------------

So, output will not toggle ,after reaching 11 state.

B) if we give 01 as input it will produce 10--11--10--11----------------

means only S (or we can say any one output) will toggle , but not both.

C)Similar reason as B)

0 votes
0 votes
The answer Is surely D, but i will try to give the proper reason as far as i know about this concept.... SR flip flop with NAND gate has memory state at 11 and indetrminate state at 00.

Now what actually meant by INDETERMINATE STATE is that on application of 00 both Q and Q' both become 11. Well thats not a problem but problem is when we apply input combination 11. On application of input combination 11(which is a memory state) either Q becomes 1 and Q' becomes 0 or vice versa which in fact is actually INDETERMINATE, Because it depends on the delay of the 2 used NAND gates. That NAND gate which has minimum delay will lead its output to 1 and NAND gate with higher delay will lead its output to 0. So, this output combination is not fixed and will be different in different circuit. so, this way the input combination 00 is indeterminate.

Now if  both NAND gates and the associated wires have the same delays, both outputs will oscillate indefinitely with a period of 2 gate delays.And Thats the case when  RS Flip flop may oscillate.

So yes once again answer is D
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