Throughput of the Pipeline

Question

Consider a machine with 10 ns clock and it takes 4 clock cycle per ALU instruction, 5 clock cycle per branch instruction, 6 clock cycle memory instruction. There exists 40% ALU instruction, 20% branch instruction, and 40% memory instruction. What is throughput of pipeline system if overhead is 2 ns? ______________ MIPS (integer value only).

Comments

i am new to this

anyone plz explain what mips value tells

Answer 1

Normal average execution time = (0.4 * 4 + 0.2 * 5 + 0.4 * 6) * 10ns = 50 ns.

So, $MIPS = \frac{10^{-6}}{50 \times 10^{-9} } = 20.$

Clock time with pipeline = 10 + 2 = 12 ns.

The no. of cycles are different for ALU, branch and memory instructions. But do they affect pipeline throughput? - depends on data and structural hazards.

Do branch instruction affect pipeline- yes and depends on branch prediction and how much delay each branch causes. I'm not able to calculate this based on information in question (where is the question from?)

Assuming everything is neglected or included in overhead, with pipeline we complete 1 instruction every clock cycle. i.e.,

$MIPS = \frac{10^{-6}}{12 \times 10^{-9}} = 83.33$.

Comments

question is from madeasy test.

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i too was confused how to calculate . well answered.

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if the answer is 83.33 why we are taking 83 not 84?

Is it for the reason that 83.33 means complete execution of 83?

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If its average 83.33 makes sense, but if we say completed we can take floor. Nowadays they will be giving marks like 83-84 in GATE, so no issues :)

Answer 2

83 MIPS

Avg time for 1 instruction non pipeline= (40% * 4 + 20% * 5 + 40%*6)10 ns =5* 10 ns =50 ns
Avg time for 1inst in pipeline would be just 10 +2 = 12 ns
12 ns --> 1 inst

1 sec ---> x inst

x= $\frac{1}{12}*10^{9} = 83 MIPS$

Answer 3

let us assume 100 instructions..

latency of each stage=10+2(overhead)ns=12ns

now total memory access time=(40*4+20*5+40*6)*12ns=6000ns

6000ns------>100 instruction

1 sec---->100/6000*10^-9=100/6 *10^6=16.67MIPS

throughput=16.67 MIPS