Write Back and Write Through

Question

A 64 word cache and main memory are divided into 16 word blocks. The main memory access time is 50 ns/word and the cache access time is 10 ns/word. Hit ratio for read operation is 80% and for the write operation is 90%. Whenever a cache miss happens, associated block must be brought from main memory to cache for both read and write operation. Let there be 40% references for write operations.

1) What is the throughput of the memory system for write through policy?

2) In the above problem if write back updation is used and at any point of time 30% cache blocks are modified, What is T_avg in write back policy?

Ans for :

1) is 6.5 Million words/sec

2) is 176.4 ns

Comments

@ sushmita ,i think it is because we are calculating average access time, 30% cache blocks are dirty means these % of time main memory have to be updated on average .

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yes u r right. Thanks a lot.

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0.65 million/sec

Answer 1

First part answered here: https://gateoverflow.in/10668/64-word-cache-and-main-memory-is-divided-into-16-words-block

$t_m = 16 \times 50 = 800ns$ for transferring a block to cache. 

For write-back:

In write back, only when a block is being replaced from cache it will be written back to memory. And this write-back is needed only if the block is dirty. So, for both read as well as write miss, 30% of time the block must be written back to memory.

$T_{avg_R} = h_r \times t_c+(1-h_r) \times (t_m + t_c + 0.3\times t_m) \\= 0.8 \times 10 + 0.2 \times (800 + 10 + 240) = 218 ns$

Write-back avoids a memory access during a cache hit as compared to write-through. 

$T_{avg_W} = h_w \times t_c + (1-h_w)  (t_c + t_m + 0.3\times t_m) \\= 0.9 \times 10 + 0.1 \times [810 + 240] = 114 ns$

 

So, $T_{avg} = 0.6 \times 218 + 0.4 \times 114 = 176.4 ns$

Comments

Can you please explain miss cases of both read and write ?

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I have added.. Clear now?

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I will summerize what I have understood, plz check once.

Suppose CPU makes a reference for variable $x$

Read Hit : x will be read from cache

Read Miss : We look up cache for x , but fail, therefore we go to memory, fetch the block which contains x . Also there are 30% chance that x has dirty bit on so we have to write in memory those 30% of times.

Write Hit : We update the value of x in cache.

Write Miss : We look up cache for x and fail, we go to memory and bring the block containing x in cache, and again 30% chance that block has dirty bit, so we write it.

Please correct if I am wrong somewhere. 

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yes, thats perfect for write-back cache.

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Thank you :)

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What is dirty block sir?

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When a cache block is written to by CPU (any word in it), it is marked dirty so that when that cache block is removed from cache, the updates are made on main memory as well.

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@arjun sir,here in write back case,'a block' is written to main memory in case of a miss when there is 30% modification rate of cache blocks,

while for write through case in another link,'a word' is written to main memory in case of a miss

why is it so??

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@arjun sir,i understand that we need to write the dat to main memory in cas of write miss but why do we need to write a block to memory 30% of time in case of 'read miss'??

"

30% of time the block must be written back to memory.

TavgR=hr×tc+(1−hr)×(tm+tc+0.3×tm)

=0.8×10+0.2×(800+10+240)=218ns "

why are you adding 0.3 *tm in miss part of read access??

 

please clarify

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Awesome explanation

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@Arjun whys is the following equation not correct
 

Write Back Policy:
Dity Bits = 30%
Avg Read = .8*10 + .2(.3(50ns + 16*50ns + 10ns) + .7(800ns + 10ns)
         = 8 + .2(.3*860ns + .7(810ns))
         =8 +.2(258+567)
         =8+165ns= 173ns

Avg Write:
        =.9*10ns + .1(.3(50ns + 16*50ns + 10ns) +.7(800ns +10ns))
        =9 + .1( .3*860ns + .7(810ns))
        =9+.1*825
        =91.5
Avg AT = .4*91.5 +.6*173ns

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@vijay

read this thread

https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial

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Hi,

In the question it's mentioned "30% cache blocks are modified" and not 30% probability that it is modified.

The question is solved using the latter.

If we consider the former we would have to do 0.3 * 4, no? (Since there are 4 blocks -- >64/16)

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@Arjun  SIR @ Bikram  SIR I HAVE A DOUBT THAT WHEN TO CONSIDER CLEAN BITS IN SOLUTION AND  WHEN TO NOT BECZ HERE CLEAN BITS ARE NOT CONSIDERED  PLEASE TELL WHY ??

AND WHAT SHOULD BE GIVEN  IN QUESTION SO THAT WE CAN USE PERCENTAGE OF CLEAN BITS????

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@eyeamgj

$T_{avg_{R}}$=$h_r×t_c+(1−h_r)×$[% dirty bit $(t_m+t_m+t_c)$+% clean bit$(t_m+t_c)$ ]

$T_{avg_{W}}$=$h_w×t_c+(1−h_w)×$[% dirty bit $(t_m+t_m+t_c)$+% clean bit$(t_m+t_c)$ ]

these are same as Arjun sir has given ,when you further  solve these ,these can be reduced to 

 $T_{avg_{R}}$=$h_r×t_c+(1−h_r)×$[% dirty bit $(t_m)+t_m+t_c$ ]

$T_{avg_{W}}$=$h_w×t_c+(1−h_w)×$[% dirty bit $(t_m)+t_m+t_c$]

 

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@Arjun sir @Bikram sir

Why in write back we are not considering write time to find TavgW incase of write miss.

I.e. TavgW= h*TC + (1-h)*(Tc + Tmbo+ Tmbn+Tw)

TC is cache access time

Tmbo is time to replace old dirty block

=X* Tmemory block access time

Where X is fraction of block dirty

Tmbn = To bring new memory block.

Tw is to update cache and main memory for miss= max{ Tword updation in cache ,Tword updation in mainmemory}

In case of write through we are considering memory write and main memory block movement separately.

I.e...TavgW=hw×tm+(1−hw)(tm+800)

Here Tm is memory word write time

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@Arjun sir

what is the meaning of writeback in case of read ,why are you using 0.3*Tm is read case.

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what is the meaning of this line "Also there is a 30% chance that x has a dirty bit on so we have to write in memory that 30 % of times."

why a block which is fetched from the main memory has a dirty bit. Please clear my doubt.

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Help please! .. in case of read miss

Accessi cache(miss) + accessing mm (to store the block)  +accessing cache[to retrieve dirtydata ] + accessing mm[to store 30% of data]..

Why here yellow one is neglected..

Literally need help

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@Subbu.  What’s the source of that equation?

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Could you please tell me!.. how can we read and write dirty blocks with out accessing cache ... please sir since two days it's really shattering my concepts... If my intuition is wrong please tell me what is goin on please sir @Arjun

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Which book are you following for COA? I guess ‘no book’

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Yes sir!.. could you please tell me ..... I can understand if you tell it in anydepth

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First do it from standard book. Then you won’t have to “shatter your concepts”. You are simply wasting your time trying to answer these questions without knowing the basics. After seeing from book these slides also will be useful: https://web.stanford.edu/class/archive/ee/ee108b/ee108b.1082/handouts/lect.12.Memory.pdf

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How can I missed  this ,it's all about one word --parlell!.. Thanks sir