Gate 2016 syllabus C.O. memory interface

Do we need to practise memory interfacing (not given in syllabus) questions? but people are actively answering questions here on memory interface. If yes, what types migh...

resilientknight

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resilientknight asked Aug 16, 2016

CO and Architecture
memory-interfacing

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0 votes

1 answer

Jeetmoni saikia asked Oct 11, 2022

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The number of address lines required to address 8 GB memory is a) 8 b) 1024 c) 32 d) 33 . Please help

Jeetmoni saikia

896 views

Jeetmoni saikia asked Oct 11, 2022

CO and Architecture
co-and-architecture
digital-logic
memory-interfacing

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4 votes

2 answers

LavTheRawkstar asked Nov 26, 2016

16,035 views

coa morris mano numerical cache memory gate also important
A digital computer has a memory unit of 64K x 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of 4 words. a. How many bits are there in the tag, index, block and word fields of ... of the cache, and how are they divided into functions? Include the valid bit. c. How many blocks can the cache accommodate?

A digital computer has a memory unit of 64K x 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of 4 words.a. How many bits are there in ...

LavTheRawkstar

16.0k views

LavTheRawkstar asked Nov 26, 2016

CO and Architecture
co-and-architecture
memory-interfacing

+ –

0 votes

1 answer

zeeshanmohnavi asked Dec 26, 2018

475 views

MadeEasy Test Series: CO & Architecture - Memory Interfacing
Consider a DRAM that must be given a refresh cycle $64$ times per msec. Each refresh operation requires $100 \ nsec$ and a memory cycle requires $200 \ nsec$. The percentage of the memory’s total operating time must be given to refresh is _______ (upto $2$ decimal places)

Consider a DRAM that must be given a refresh cycle $64$ times per msec. Each refresh operation requires $100 \ nsec$ and a memory cycle requires $200 \ nsec$. The percent...

zeeshanmohnavi

475 views

zeeshanmohnavi asked Dec 26, 2018

CO and Architecture
co-and-architecture
made-easy-test-series
memory-interfacing

+ –

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