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+9 votes

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S - R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.

 ADD  R5, R0, R1  ; R5 → R0 + R1
 MUL  R6, R2, R5  ; R6 → R2 * R5
 SUB  R5, R3, R6  ; R5 → R3 - R6
 DIV  R6, R5, R4  ; R6 → R5/R4
 STORE  R6, X  ; X  ← R6


The IF, ID and WB stages take 1 clock cycle each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is

  1. 10
  2. 12
  3. 14
  4. 16
asked in CO & Architecture by Veteran (20.8k points)  
retagged by | 2.2k views

3 Answers

+28 votes
Best answer

This is what i have solved. so answer is 12

answered by Boss (6k points)  
selected by

First of all thanks a lot for such a detailed explanation.

Actually for point A doubt is not split phase access,I am saying I3 can go in ID stage in 4th cycle and remain there till 6th.Why is this wrong?


ur doubt is,



and not 

The reason is -- only in the 3 rd Execute stage of I2 data will be ready which I3 is trying to get from I2... If I3 is able to get the data at first Execute itself, then there is no need of 2 nd execute and 3 rd execute for I2. I2 needs 3 clock-cycles for execute(ALU) means the result of that ALU operation will be available only in the    3 rd execute stage...  

i2 E E E
i3 ID ID


Now, I am saying why can't I3 remain in ID stage till 6th cycle and access reg file in 6th cycle itself.

I mean to say I get your point but whats wrong in the way I am thinking.

@Vicky rix

@VS  I3 only needs 1 ID stage .. then why are you extending it to 3 clock-cycles ??? 

Let us assume it is given in question that I3 needs 3 ID stages, still we cant do as you have drawn because we always start ID only after EX finishes.. And here we finish EX in the 1 st half of 6 th clock-cycle only after that ID can start ... Also note that our computer doesnot know whether ID will need 1 clock-cycles or 2 clock-cycles or 3 clock-cycles... So we always start our "data getting stage of an instruction" only after "data giving stage of an instruction" finishes...


I3 needs only one ID stage thats right.But an instruction can surely wait in a state until the next stage is available.So,I3 can be in ID stage for 3 clock cycles.

(PS: This waiting thing you can also check in other gate previous year questions and also there have been extensive discussions on this topic here in GO.Now,I don't exactly remember the question but i have read it somewhere,specially something Multiple buffers concept.)

Can you provide some reference for your comment  :

ID start only after EX finishes.

+14 votes

answer = option D = $16$ cycles are required

answered by Veteran (28.7k points) .

This one . And I was asking  the reason for the same .  How do we generalise  split phase occurs or not !


I got this reviewed from a professor at IIT. He says assume split phase in case of operator forwarding if nothing is mentioned explicitly. He says it will be mentioned if the operator forwarding does not happens in the same cycle (which actually should be from the definition of operator forwarding ) otherwise you can challenge the question
Split phase access even for EX stage? Which IIT prof. said this?
okay, so what we should consider ?16 or that ex-ex forwarding to get 12? in GATE?
I could have chosen 16 in hurry. But after reading comments i can see there is nothing clear. However, i think ID should come in the same cycle as EX because EX stage is also including Data Memory phase. May be this is some kind of hint to choose 12 as answer.
+2 votes

Hi  , I have a very silly doubt here. 


Can we do the IF stage as I did ? because in other answers I could see , IF is also done after EX


srestha goel 

I have the confusion here that , IF stage of I4 instruction , can I start it in clock 4 ? because anyhow , ID should be started at  clock 7. or does IF also needs to start at clock 6 ?

Please clarify this doubt.



(N.B : please bear with my poor , illegible hand-writing )


answered by Boss (5.6k points)  
edited by
Answer given to this question is 14

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