Virtual Gate Test Series: CO & Architecture - Pipelining Comparision

Question

For D1
1st instruction will take 3+2+4+2+3 = 16ns
rest 99 instruction will take 99*4=396
Hence total: 16+396=412

For D2
1st instruction will take 2+2+2+2+2+2+2+2 = 16ns
rest 99 instruction will take 99*2=198
Hence total: 16+198=214

Hence, 412-214=198 according to me

Where am I going wrong?

Comments

gate question... check out solution from prev years.

Answer 1

u have taken everything right . But u missed that in a pipeline . the clock is set such that the maaximum stage can complete . so in the starting 1st instruction everything will be 4ns . = 20ns .
20+396 = 416ns
416-216= 202 ns .

Comments

So, if in D2, if all were not of 2ns, if say 7 stages were 2ns and 1 stage was 3ns, then we would get:

3*8+99*3? right?

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right . prefer using formula

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What happens in case of asynchronous processors?

Answer 2

D1:
k = 100 , 5 stages , Stage Latency = 4ns
Total Time = (k+n-1)*t = (100+5-1)*4 = 104*4 = 416 ns

D2 :
​k = 100 , 8 stages , Stage Latency = 2ns
Total Time = (k+n-1)*t = (100+8-1)*2 = 107*2 = 214 ns

Time Saved = 416 - 214 = 202 ns
 

Comments

Yes, the direct formula is giving the right ans. But I am confused where I am going wrong

Answer 3

answer is 416-214=202

Answer 4

In D1

Total time=Time taken to executes 1'st instruction + 99 x 1 stages x Td1

T1=1 x5 x4 + 99 x4=416

Similarly for D2

T2= 1 x 8 x 2 + 99 x 2=214

T1 - T2= 202ns