In this question PC and GPR are carried out in the ALU.
So, PC and GPR performing write operation.
"call Rn, sub” - here subroutine call is performing , which is a memory read operation
And each memory read operation takes 2 clock cycle.
Then operation is performed in ALU.
Next operation will be
Rn <= PC + 1;
PC <= M[PC];
i.e. PC is incremented which requires no clock cycle.
Next PC value will be that memory location and according to the question it is a write operation. It is the 3rd step of Fetch cycle. So, it requires 1 clock cycle.
Total 3 clock cycle