ISI2015-PCB-CS-6a

Question

Consider the following timings for a five-stage processor pipeline (these timings include the latching overhead):

$$\begin{array}{ll} \text{Fetch} & 305 \text{ ps} \\  \text{Decode} & 275 \text{ ps} \\   \text{Execute} & 280 \text{ ps} \\  \text{Memory} & 305 \text{ ps}  \\ \text{Write Back} & 250 \text{ ps}  \\ \end{array}$$

1. Given the timings for the datapath stages listed above, what would be the clock period for the entire datapath?
2. In a pipelined datapath, assuming no hazards or stalls, what will be the throughput (instructions per second) in steady state?
3. Assuming that $N$ instructions are executed, and that all $N$ instructions are add instructions, what is the speedup of this pipelined implementation compared to a nonpipelined implementation? Assume that each add instruction consists of Fetch, Decode, Execute and Write Back.

Answer 1

1. Clock Period $=$ max (Stage Delay) $= 305$ps
2. Throughput $= 1/305$ ps $= \frac{10^{12}}{305s} = \frac{10^6}{305} \text{ MIPS} =3.278$ Billion instructions/second
   (Steady state means number of instructions is very large and so we neednot caonsider the pipeline fill and pipeline case)
3. SpeedUp $=$ (Time without Pipeline) $/$ (Time taken with Pipeline)
   $= N*(305 + 275 + 280 + 250)/(4 + N - 1)*305$
   $= 3.62*N/(3+N)$

if $N$ value is very large then $N$ and $N+3$ are approx same.
for large value of $N$ Speed Up will be $3.62$.

Comments

can u please explain in throghput, how u calculated 32.78 MIPS from 1/305ps.Please explain?

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#Instructions = 1/max clock cycle time = 10^12/305 = 3.278 * 10^9 = 3.278 billion instructions/sec

Speedup = (305 + 275 + 280 + 250)/305 = 1110/305 = 3.64

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Throughput is wrong

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Part iii) is wrong. Even if your instructions are not using the MEM stage, as your pipeline has this stage, the instructions will stall on this stage. So speedup will be 4.64 as mentioned in other answers.

Answer 2

a)) Clock period of entire datapath= max of all time period=305pesc

b)) Through put will be number of instruction executed per second

So through put=1/305ps=32.78 million instruction per second

c)) 

Speed up= Twp/Tp

Twp(Time taken without pipeline)=n*(305+275+280+305+250)

Tp=1 x 4 x 305 + (N-1) x 305 x 1

Speed up=Twp/Tp

Speedup=1415N/305N+915

if N is infinite or very large

Speed up=4.64

Comments

If all instructions are add then we will not use mem access stage in pipeline and nonpipeline .

Is it the concept of the third one?

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can u please explain in throghput, how u calculated 32.78 MIPS from 1/305ps.Please explain?

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How can the above answers vary just for large N?
The answer above you got 3.62, please tell how to solve such problems?

Answer 3

1. Clock Period == maximum stage Delay =305ps
2. Throughput =1/305ps
3. Let n =100 instructions.
1st instruction will take 5 clock cycles and remaining 99 instructions will take 1 clock cycle. 
Therefore, 1*5*305 + 99*1*305 = 31720

Now in non-pipelined processor, 100*(305 + 275 + 280 + 305 + 250) = 141500

Speedup = 141500/31720 = 4.46
If you increase the value of n than answer may vary.