(1) Memory Capacity = 221 bits
RAM chip capacity = 2K * 8 bits = 214 bits
So, number of RAM chips required = 221 / 214 = 27 = 128
(2) Memory needs to address each word.
A word is 4 bytes. So, number of possible words = 221/(4*8) = 221/25 = 216
So, number of address lines needed for memory = 16
(3) A RAM chip has 2K rows of cells to select (each row has 8 cells of 1 bit each which will always be selected together).
So, we need 11 bits to select any of these 2K rows.
(4) 16-11 = 5 address lines will be used to select the appropriate RAM chip(s)- 5 address lines to select 128 chips doesn't seem logical but this is how multi-byte words can be fetched from memory in parallel. At any time 4 RAM chips will be selected together and a byte can be fetched in parallel from all these, resulting in 4 bytes being fetched in 1 memory cycle. (See (s) in the question)
(5) We use 5 address lines to select the RAM chips. So, decoder needs to be 5 to 32.
(A) choice.