$\underline{\textbf{Answer}\Rightarrow}$ None is the correct answer here.
Option $\mathbf{(D)}$ should be both edge as well as level triggered.
$\underline{\textbf{Answer}\Rightarrow}$
$\mathbf{8085}$ has $\mathbf 3$ $\color{blue}{\text{maskable}}$ vectored interrupts $\textbf{(RST 7.5, RST 6.5 and RST 5.5)}$, $\color{magenta}{\text{one non-maskable}}$ interrupt (TRAP), and $\color{green}{\text{one externally serviced interrupt (INTR)}}$.
$\mathbf{RST\; 5.5}$ interrupt is edge triggered (latched)
$\mathbf{RST\; 5.5}$ and $\mathbf{6.5}$ are level sensitive.
$\mathbf{TRAP}$ Both edge as well as level triggered to avoid false interrupt.
https://en.wikipedia.org/wiki/Intel_8085
https://electronics.stackexchange.com/questions/21886/what-does-edge-triggered-and-level-triggered-mean