As machine has $4$ registers, $\log_2 4 = 2-bits$ are required for register identification.
we have 8 bits for an instruction.
given that LDC has a immediate operand of size 7 bits ==> we left with 1 bit to identify this instruction
∴ assign 0 or 1 to it and fix it ! ( i preferred 0 and i am filling the bits from Right to Left, i.e., MSB → LSB )
For remaining type of instructions 1$^{st}$ bit is fixed to 1.
BRA,BZ, and BNE instructions takes 5 bits as offset.
to uniquely identified these operations we need atleast 2 bits, but there are more combinations with them, So remaining were used to identify some other instructions.
So, Fix the 2$^{nd}$ and 3$^{rd}$ bits as
00 ---> for BRA
01 ---> for BZ
10 ---> BNE
11 ---> to continue decode remaining instructions
MOV copies any register into any other register. ====> instruction like MOV R$_i$,R$_j$
for this instructions operands takes 2+2=4 Bits, already first 3 bits are fixed, Keep 0 at 4$^{th}$ bit from MSB.
Now remaining option is Keep 1 at 4$^{th}$ bit from MSB.
Remaining instructions are
Load R$_i$
Store R$_i$
Add R$_i$
Sub R$_i$
all these instructions are take 2 bits for operand ==> Reserve at LSB bits.
remaining size we have = first 4 bits fixed from MSB and Last 2 bits fixed ==> in the middle, we have 2 bits remaining
we have 4 instructions ( i.e., Load,Store,Add,Sub ), which requires 2 Bits ==> fix them
00 ---> ADD
01 ---> SUB
10 ---> LOAD
11 ---> STORE
The instruction format is: