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Consider the logic circuit given below.

The inverter, AND and OR gates have delays of $6, 10$ and $11$ nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for $\text{Q}$ before it becomes stable?

  1. $5$
  2. $11$
  3. $16$
  4. $27$
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25 votes
I think the answer is A. 5.

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns.

Correct me if I am wrong.
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If we ignore delay of exor gate then total delay is 16 . NOT and OR gate running independently but AND gate can't run until  NOT gate give output to AND gate.So NOT and AND are working sequencially . so (6+10) total delay.
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'inverter' and 'or' gate starts at the same time while 'and' gate waits for 'inverter' output.

# - 'inverter' and 'and' gate are serially connected so time required is 6+10=16ns.

$ -'or' gate requires 11ns.

# and $ is parallely connected so total time required is max(#,$) =max(16,11) =16ns.

Total time required is 16ns.

(i am not sure...its my answer)

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Inverter and AND gate will take total of 6 + 10 = 16 ns. (one after another)

OR gate will take 11 ns.

before 11 ns there was no glitch(fault) as none of inputs has reached to X-OR

now at 11th ns input from OR gate reaches to X-OR and yet there is no other input to X-OR

This glitch(fault) will remain till 16th second when output of NOT-AND appears as input to X-OR

Then X-OR will operate normally 

so glitch was from 11th to 16th ns $16-15 = 5ns$

Answer:

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