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Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2$ gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is

  1. $3.2$
  2. $3.0$
  3. $2.2$
  4. $2.0$
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OPtion A is Correct

Speed up = Time without pipeline / Time with pipeline

Time without pipeline= 4 clock cycle

1 clock cyle = 1 / (2.5 *10^9)

Time with pipeline = 1 clock cycle in ideal case

1 clock cycle= 1/ (2 * 10^9)

 

so, speed up= (4 * 1 / (2.5 *10^9)) / 1/ (2 * 10^9)

CORRECT ANS is 3.2
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Let consider 100 instruction

=>For a non pipeline processor

Each instruction take 4 clock cycles

so, 100 instructions take 4*100=400 clock cycles

Frequency is 2.5*109Hz so 1 clock cycle=1/(2.5*109)=0.4 ns

so Time in Non pipeline processor=400 clock cycles=400*0.4=160ns

=>Now, for a pipeline processor

very first instruction takes 5 cycles,since 5 stage pipeline

No stalls is given ,so 99 instructions will take 1 clock cycle each,so total clock cycles=5+99=104 clock cycles

Frequency is 2Ghz,so 1 clock cycle=1/(2*10^9)=0.5ns

so Time in pipeline processor=104 clock cycles=104*0.5=52ns

==>Speed Up=160/52=3.0

Answer:

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