Pipelining

Question

You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI(cycle per instruction) of 1.4.The designers pipelined it into 5 stages with stage timing of 1ns,1.5ns,4ns,3ns,0.5ns, Each pipelined stage added also adds 20ps due to resister setup delay.If pipeline stalls 20% of the time for 1 cycle and 5% of time for 2 cycles(these occurrences are disjoint).what is speedup compared to the original processor?

Comments

speed up = 2.05 is the answer ?

Answer 1

Time to execute one instruction in when non-pipelined = old_CPI * cycle_time = 1.4*10

After pipelining the same architecture :

CPI will increase from 1.4, because of stalling in the pipeline as given in the question.

Calculate stalls per instruction : $0.2*1 + 0.05*2 + 0.75*0 = 0.3$

So, avg CPI = original base CPI + stalls per instruction = 1.4 + 0.3 = 1.7

In this case Time to execute one instruction ( piplined ) = new_CPI * cycle_time = 1.7 * (4ns + 20ps) = 1.7*4.02

SPEED_UP = $\frac{1.4*10}{1.7*4.02} = 2.048$

Comments

I could not remember the solution site ! but there they have written that we could take both ! and we normally take 1. agree

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As we know, if a stall is for say 1 then CPI =2

if a stall=2 then CPI =3

so by that avg CPI= 0.2*2+0.05*3+0.75*1=2.65

so then the solution is coming different...why?

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2015 set 1 pipeline question will give you response for considered base CPI to 1