You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI(cycle per instruction) of 1.4.The designers pipelined it into 5 stages with stage timing of 1ns,1.5ns,4ns,3ns,0.5ns, Each pipelined stage added also adds 20ps due to resister setup delay.If pipeline stalls 20% of the time for 1 cycle and 5% of time for 2 cycles(these occurrences are disjoint).what is speedup compared to the original processor?