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Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The $\textsf{MUX}$ is of size $8 \times (2:1)$ and the $\textsf{DEMUX}$ is of size $8 \times (1:2)$. Each memory operation takes $2$ $\textsf{CPU}$ clock cycles and uses $\textsf{MAR}$ (Memory Address Register) and $\textsf{MDR}$ (Memory Date Register). $\textsf{SP}$ can be decremented locally.

The $\textsf{CPU}$ instruction "push r" where, $r =$ $A$ or $B$ has the specification

  • $M[SP] ← r $
  • $SP ← SP - 1$

How many $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction?

  1. $2$
  2. $3$
  3. $4$
  4. $5$
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3 votes
3 votes
I think this requires 3 clock cycles :

As Arjun sir said,for write operation, the data must be in MDR and address must be in MAR.

1 cycle required to load the SP into MAR (since SP and MAR are directly connected i,e no bus required) and simultaneously move the data to MDR (we need bus access here)

2 cycles required to load the data of MDR into the address the memory indicated by MAR (since it is given 2 mem cycles are required for each memory operation)

And SP can be decremented locally so no mem cycle required (we can do this during memory operation)
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3Cycles to load the MAR from SP as the bus is of 8bit but address is of 16bit and it  is non pipelined

 To load the data from one of the registers to MDR we dont need additional cycles , can be done within this 3 cycles above .SP can be decremented locally so we dont need additional cycle for it.

2cycles to write the data into memory.

Therefore total 5 cycles.
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Answer:A

Because SP is store in MAR(it's a register there is no clock cycle needed for this)

M[MAR] <--r(A/B)  store the value in memory only need two clock cycle
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Answer (B)

3 clock cycles are needed

T1: MAR <- SP  // Bits in even positions are moved to MAR

T2: MDR <- r,  MAR <- SP  // Bits in odd positions are transferred to MAR

T3: M[MAR] <- MDR

At T2, Since the MAR and SP are connected directly through MUX/DEMUX and hence Data Bus is free to perform MDR <- r operation which requires 8 bit data bus and hence we can overlap these 2 operations. 
Answer:

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