I am assuming cache physically addressed cache.
A). TLB hit, cache hit:
1 + 1 = 2 cycles
B). TLB miss, page table hit, cache hit
1 + 5 + 1 = 7 cycles (When there is a miss in TLB, page table which is in main memory is accessed)
C). TLB miss, page table miss, cache hit
When page table misses, cache hit cannot happen. Because when a page fault happens, we shouldn't check the cache as it won't be having the data.
D). TLB miss, page table hit, cache miss
1 + 5 + 1+ 5 = 12 cycles
E). TLB miss, page table miss
1 + 5 + 100 + 1 + 1 = 108 cycles
Average memory Access time =>
=> $0.95 \left(1 + \underbrace{0.90 \times 1}_{\text{cache hit}}+\underbrace{0.10 \left(1+5\right)}_{\text{cache miss}}\right) \text{(TLB hit)} \\+ 0.05 \left(1 + 0.99 \left(5 + \underbrace{0.90 \times 1}_{\text{cache hit}} +\underbrace{0.10\left(1+5\right)}_{\text{cache miss}}\right)\right)\text{(TLB miss, page hit)} \\ + 0.05\left(1+ 0.01 \left(5+100+\underbrace{1+1}_{\text{access restarted}}\right)\right)\text{(TLB miss, page fault)}$
=> 2.375 + 0.37175 + 0.1035
=> 2.85025 = approx 3 cycles.