Consider the unpipelined machine with 12ns clock cycles. It uses 4 cycles for ALU operations and branches, whereas 5 cycles for memory operations. Assume that the relative frequencies of their operations are 30%, 20%, 20% repectively. Suppose that the due to clock skew and setup, pipelining the machine adds 1ns overhead to the clock. How much speed up in the instruction execution rate will we gain from a pipleline ?
a) 2.0 times b) 3.1 times c) 2.8 times d) 3.5 times