a) Pipeline contains 5 stages: IF, ID, EX, M and W;
b) Each stage requires one clock cycle;
c) All memory references hit in cache;
d) Following program segment should be processed:
// ADD TWO INTEGER ARRAYS
LW R4 # 400
L1: LW R1, 0 (R4) ; Load first operand
LW R2, 400 (R4) ; Load second operand
ADDI R3, R1, R2 ; Add operands
SW R3, 0 (R4) ; Store result
SUB R4, R4, #4 ; Calculate address of next element
BNEZ R4, L1 ; Loop if (R4) != 0
Calculate how many clock cycles will take execution of this segment on the regular (non pipelined) architecture ?