total cycle time in non-pipeline

Question

a) Pipeline contains 5 stages: IF, ID, EX, M and W;
b) Each stage requires one clock cycle;
c) All memory references hit in cache;
d) Following program segment should be processed:
// ADD TWO INTEGER ARRAYS

LW R4  # 400
L1: LW R1, 0 (R4)  ; Load first operand
LW R2, 400 (R4)  ; Load second operand
ADDI R3, R1, R2  ; Add operands
SW R3, 0 (R4)  ; Store result
SUB R4, R4, #4  ; Calculate address of next element
BNEZ R4, L1  ; Loop if (R4) != 0

Calculate how many clock cycles will take execution of this segment on the regular (non pipelined) architecture ?

Comments

400 is immediate data not any memory address that's why. That means no operation is getting performed in memory phase of I1. we are writing 400 in register that means register content getting updated in WR phase so we will have to wait for its completion.

In memory phase of I2 we need contents of R4 and correct value R4 will be available after WR phase of I1

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okay,i got that.

ut can yo pls tell me why are you doing this-

no. of cycle in loop = 22-13

whts the logic??

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number of cycles between two loop execution = 2nd loop last cycle - 1st loop last cycle

Answer 1

Each instruction have 5 stages and each stage requires 1 clock cycle

So clock cycles required for 1 instruction = 5

Now the loop is running for 100 times since we are decrementing by 4 each time

There are 6 instructions in the loop.

Non pipeline means we have to execute sequentially

So total time require for execution = 1 * 5 + 6 * 5 * 100 = 5+3000 = 3005 clock cycles

Comments

http://www.ee.ryerson.ca/~lkirisch/coe818/midfin/Solutions_COE818_MT.pdf

second problem