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This is the circuit diagram of Carry Look ahead adder.

We can divide 3 levels to find total delay

In level1 delay max(EXOR,AND) gate=max(x,y)

level2 delay max(EXOR,AND)=max(x,y)

level3 delay OR gate delay=z

Now, total of these 3 are the delay of carry look ahead adder

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For a 4 bit CLA, Assuming XOR delay = 20 , AND delay = 10, OR delay = 10
 

Answer:

4 bit CLA takes maximum time to get the carry C4 = C0P0P1P2P3+G0P1P2P3+G1P2P3+G2P3+G3

In this whole term C0P0P1P2P3 takes maximum time.

If AND fan-in is 2 then for C0P0P1P2P3 it needs 3 levels. so time = 20(XOR) + 3*10(AND)

If OR fan-in also 2 then it also takes 3 levels(as there are 4 terms) = 3*10

So total time is 20+30+30 = 80ns

Correct my if i made any mistake..

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