GATE CSE 2015 Set 2 | Question: 48

Question

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is $1.2$ microseconds. A $4$-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this $4$-bit binary adder in microseconds is ______.

Comments

In Ripple carry adder, a stage doesn’t wait for the “full output” of previous stage. It only waits for the previous stage’s carry to reach to itself. Now, carry generated by our current stage can be written in 2 ways:-           

  1)Carry generated= $xy + $ $(x$$\bigoplus$$y)C_{in}$                2)Carry generated=  $xy+yC_{in} +xC_{in}$       where $C_{in}$ is carry received by our current stage

Using 1st way, delay in carry generation would be 4.8$us$  and  by using 2nd way, delay in carry generation would be 2.4$us$. So, answer should be according to 2.4$us$ delay(better than 4.8$us$ delay).

So, total delay will be $(4-1)*2.4 + 4.8$ = $12us$

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what will be the answer if it is carry look ahead adder?

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@swami_9

I think it will be $4.8\mu s$ only, as there is no need to wait for the carry from the prev. adder.

Answer 1

Diagram shows flow of input to output along with delay at each level ; for understanding 

Answer 2

Circuit diagram for the problem can be made as:

delay for XOR gate = 2*1.2 = 2.4 μs.

delay for AND/OR gate = 1.2 μs.

First XOR gate takes 2.4 μs. and meanwhile XY can be calculated in parallel. Similarly, Second XOR gate takes another 2.4 μs and in the meanwhile output of AND(1.2 μs) and OR(1.2 μs) can be calculated (Since, the output of first XOR and AND is available immediately). 

So, total time taken = 2.4 + 2.4 = 4.8 μs for 1-bit calculation.

Hence, gate delay for 4-bits = $4*4.8=19.2\ μs$.

Answer 3

b) 19.2

C(i+1)=(A XOR B).C(i)+A.B

Hence Totla delay of one carry bit is 

1 XOR gate + 2 AND gate + 1 OR gate 

2.4 +1.2+1.2 =4.8 microsec.

1) total delay from c1 to c4 will be 4.8 x 4 =19.2 microsecond;

2) total delay from c1 to c3 + sum of A4 and B4 will be 4.8 x 3+ (2.4+2.4) =19.2 microsecond

hence for MAX DELAY =MAX( 19.2,192 )

MAX DELAY is 19.2 microsecond.

Comments

Even I got the same but the answer is 12 microsecond

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who told answer is $12$ ?

http://www.gate.iitg.ac.in/2015answers/CS_S06.pdf

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here, how you put the value of  2 AND gate  = 1.2ms ?

b'coz each having 1.2  for AND/OR gate

Answer 4

Kindly have a look on the Formula to compute the delay

Comments

Answer is 12.0