GATE CSE
First time here? Checkout the FAQ!
x
0 votes
92 views
Consider below code written in C  
         Loop A
sum = 0;
 for (i = 0; i < 128; i++)
for (j = 0; j < 64; j++)
        sum += A[i][j];
         Loop B
sum = 0;
for (j = 0; j < 64; j++)
for (i = 0; i < 128; i++)
                                    sum += A[i][j];
The matrix A is stored contiguously in memory in row-major order. Consider a 4KB direct-mapped data cache with 8-word (32-byte) cache lines.

The L2 cache in the Pentium 4 holds 256 KBytes of data. The cache is 8-way set associative. Each block holds 128 bytes of data. If physical addresses is 32 bits long, each data word is 32 bits, and entries are word addressable, what bits of the 32 bit physical address comprise the tag, index and offset?

i)(19,8,8)

ii)(20,8,7)

iii)(17,8,7)

iv)(18,8,6)
asked in CO & Architecture by Boss (5.9k points)   | 92 views

1 Answer

0 votes
third one is correct???
answered by (55 points)  


Top Users May 2017
  1. akash.dinkar12

    3338 Points

  2. pawan kumarln

    2108 Points

  3. Bikram

    1922 Points

  4. sh!va

    1682 Points

  5. Arjun

    1614 Points

  6. Devshree Dubey

    1272 Points

  7. Debashish Deka

    1208 Points

  8. Angkit

    1056 Points

  9. LeenSharma

    1018 Points

  10. Arnab Bhadra

    812 Points

Monthly Topper: Rs. 500 gift card
Top Users 2017 May 22 - 28
  1. Bikram

    1008 Points

  2. pawan kumarln

    734 Points

  3. Arnab Bhadra

    726 Points

  4. Arjun

    342 Points

  5. bharti

    328 Points


22,893 questions
29,196 answers
65,302 comments
27,695 users