GATE CSE
First time here? Checkout the FAQ!
x
0 votes
87 views
Consider below code written in C  
         Loop A
sum = 0;
 for (i = 0; i < 128; i++)
for (j = 0; j < 64; j++)
        sum += A[i][j];
         Loop B
sum = 0;
for (j = 0; j < 64; j++)
for (i = 0; i < 128; i++)
                                    sum += A[i][j];
The matrix A is stored contiguously in memory in row-major order. Consider a 4KB direct-mapped data cache with 8-word (32-byte) cache lines.

The L2 cache in the Pentium 4 holds 256 KBytes of data. The cache is 8-way set associative. Each block holds 128 bytes of data. If physical addresses is 32 bits long, each data word is 32 bits, and entries are word addressable, what bits of the 32 bit physical address comprise the tag, index and offset?

i)(19,8,8)

ii)(20,8,7)

iii)(17,8,7)

iv)(18,8,6)
asked in CO & Architecture by Loyal (4.7k points)   | 87 views

1 Answer

0 votes
third one is correct???
answered by (55 points)  
Top Users Feb 2017
  1. Arjun

    5386 Points

  2. Bikram

    4230 Points

  3. Habibkhan

    3952 Points

  4. Aboveallplayer

    3086 Points

  5. Debashish Deka

    2564 Points

  6. sriv_shubham

    2318 Points

  7. Smriti012

    2240 Points

  8. Arnabi

    2008 Points

  9. mcjoshi

    1696 Points

  10. sh!va

    1684 Points

Monthly Topper: Rs. 500 gift card

20,863 questions
26,022 answers
59,696 comments
22,133 users