GATE CSE
First time here? Checkout the FAQ!
x
0 votes
88 views
Consider below code written in C  
         Loop A
sum = 0;
 for (i = 0; i < 128; i++)
for (j = 0; j < 64; j++)
        sum += A[i][j];
         Loop B
sum = 0;
for (j = 0; j < 64; j++)
for (i = 0; i < 128; i++)
                                    sum += A[i][j];
The matrix A is stored contiguously in memory in row-major order. Consider a 4KB direct-mapped data cache with 8-word (32-byte) cache lines.

The L2 cache in the Pentium 4 holds 256 KBytes of data. The cache is 8-way set associative. Each block holds 128 bytes of data. If physical addresses is 32 bits long, each data word is 32 bits, and entries are word addressable, what bits of the 32 bit physical address comprise the tag, index and offset?

i)(19,8,8)

ii)(20,8,7)

iii)(17,8,7)

iv)(18,8,6)
asked in CO & Architecture by Boss (5.3k points)   | 88 views

1 Answer

0 votes
third one is correct???
answered by (55 points)  


Top Users Mar 2017
  1. rude

    5236 Points

  2. sh!va

    3054 Points

  3. Rahul Jain25

    2920 Points

  4. Kapil

    2732 Points

  5. Debashish Deka

    2602 Points

  6. 2018

    1574 Points

  7. Vignesh Sekar

    1430 Points

  8. Bikram

    1424 Points

  9. Akriti sood

    1420 Points

  10. Sanjay Sharma

    1128 Points

Monthly Topper: Rs. 500 gift card

21,549 questions
26,889 answers
61,248 comments
23,251 users