Average seek time = 6ms
Average rotational delay = 3ms
Data transfer rate = 30MB/sec
All disk accesses are 8KB of data. Here, they are assuming that whenever disk is accessed, it either reads or writes 8KB of data.
Data bus width is given to be 32 bits and a bus transfer to / from MM takes 10 ns.
A). Memory Bandwidth is the rate at which data can be read or stored into the memory. Also, known as MM transfer rate.
Transfer rate according to the question for a disk = 30MB/sec.
It is also given that 32 bits can be carried by the bus to the main memory in 10 ns, hence, what is the MM transfer rate then ?
MM tramsfer rate => 32 bits / 10 ns = 400 MB/sec
- Now, a disk can transfer 30 MB in a sec whereas, MM can attain upto 400 MB/sec, hence, maximum disks that can transfer simultaneously = 400 / 30 = 13.333.
- If I take it as 14 (approx) , then total rate will be 420 MB/sec, which is out of scope for MM .
- So, at the best, 13 disks are capable of transferring simultaneously .
B). Question asks about using burst mode approach to be used to transfer 8KB of data.
So, for accessing 8KB of data, how much time is needed :
=> Time to find the specific track (seek time) + Time to reach the specific sector on the track + Time to transfer 8KB of data (Here, Average seek time and Average rotational delay are given, so will assume directly these times)
=> 6 + 3 + (8KB / 30MB/sec)
=> 9.26666
=> 9.27 ms
This says, that in a time period of 9.27 ms, 8KB of data can be accessed on the disk.
But, we need to access the given data using cycle stealing. DMA controllers operate in a cycle stealing mode here particularly in which they take over the bus for each byte (word) of data to be transferred and then return the control to the CPU.
How this mechanism works ?
- CPU provides the start address and the word count to DMA controller, and the word count specifies the data to be transferred in one cycle stolen .
- And each time the disk is ready to transfer a byte, it asserts its DMA request line to the DMA controller .
- The DMA controller then, asserts the CPU through HOLD request.
- When the CPU suspends the execution of the current program, it asserts the hold acknowledge HLDA signal to the DMA controller.
- DMA controller then puts the MM address on the address bus, asserts either MEMR + IOW or MEMW + IOR on the control bus . (MEMR = Memory read, MEMW = Memory write and same for I/O )
- Disk then responds to the DMA ack. signal by reading or writing, its data to the data bus.
- And, atlast the same time, the MM responds to the control signal which causes the data to be read/written directly from/to memory.
Hence, we found that 8KB of data can be transferred in 9.27 ms.
Now, the data transfer is done by the DMA controller, which will operate at memory cycle time, so in 10 ns, 32 bits can be send.
=> 10 ns = 32 bits
=> 1 sec = 32 * 108 bits can be send.
But, data on the disk can be accessed in
=> 9.27 ms = 8KB
=> 1 sec = 6.9039 * 106 bits
Hence, percentage of memory cycles stolen by a single disk unit :
=> 6.9039 * 106 / 32 * 108
=> 0.002157 * 100
=> 0.2157 = approx 0.216 %