If u see carefully it is a 4 level implementation circuit..The 4 levels are defined as :
a) 1 NOR gate for the inputs Q and R and 2 NOT gates for input S and T : So delay of NOR gate = 2 ns and 1 NOT gate = 1 ns..So maximum of them will be considered for the overall delay in this level as for going on to next level we need that the output of this level is complete ..So delay at 1st level = max(NOT gate,NOR gate delay) = 2 ns
b) In the next level , we have MUX to which T input is selection input ..So delay = 1.5 ns
c) In the next level , after getting output of multiplexer , we get the input to the 2nd NOR gate along with P..So delay here = 2 ns
d) In the final level we have MUX which gets inputs from the outputs of previous level NOR gate and earlier MUX with selection line T' , so delay in this level = 1.5 ns
Therefore total delay of circuit = 2 + 1.5 + 2 + 1.5
= 7 ns
