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My approach is
there are 40% data access instructions, miss rate is 2%. when miss occurs CPI is 26 (as miss penalty is 25 clocks). when miss doesnt occur CPI is 2. remaining 60% intructions have CPI of 2.

average CPInew = 0.4(0.02*26+0.98*2)+0.6(2) = 2.192

please point out the mistake in this. answer for this new CPI is given as 2.7. 
kindly dont post the solution with your method, only point out mistake in my method.
thank you!!

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Given ,

CPI  = 2 when all memory accesses be it instruction fetch or operand fetch in case of Load/Store instruction is a cache hit..So it is the case where we will not have any stall..

Let us calculate effective CPI of an instruction first given the stalls
are present which is found as :


CPI(with stalls due to cache miss in both instruction and operand fetch)

= CPI(ideal) + (Cache miss rate for fetching any instruction 
            + % of load-store instruction * Cache miss rate for data operand fetch) * Miss penalty  

But here in the question only one miss rate is given , so let us assume this is both for instruction 
fetch miss and operand fetch miss = 2%

Therefore ,


CPI(new) = 2 + (0.02 + 0.4 * 0.02) * 25
              = 2 + (0.028) * 25
              = 2.7

Now let us consider the case when all instruction fetch are cache hits but operand fetch may
still be incur cache miss..So stalls will be only due to operand fetch in case of Load/Store instruction ..In that case :

CPI(with stall in operand fetch only) = 2 + 0.4 * 0.02 * 25
                                                    = 2 + 0.2
                                                    = 2.2

Therefore , % enhancement over the first case = ((CPI in 1st case - CPI in 2nd case) / CPI in 1st case) * 100

                                                                    = (2.7 - 2.2) / 2.7

                                                                    = 18.51 % 

Hence new method is 18.51 % more faster as compared to earlier one..

Reference : Performance evaluation topic (Section 6.8) of Hamacher Zaki which has cache miss scenario also

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