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Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it to the main memory over a bus. The latency of access of both memories is 80ns each. The bus is clocked at 100 MHz, and in each bus cycle, one bus transfer is completed. The bus and both memories are 16 bytes wide each. How long does it take to complete the transfer? All possible pipelining between stages is implemented.

   
   
 

(A) 10250ns

 

(B) 10330ns

 

(C) 10360ns

 

(D) None of these

1 Answer

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Number of transfers [i.e. each of 16 byte in one cycle.]= $\frac{2048}{16} = \frac{2^{11}}{2^{4}} = 128$ transfers Each of 16B

Time for Bus Cycle $\frac{1}{100MHz} = 10 ns$ .

Time for reading 128 transfer packets = 128 $\times$ 80ns = 10240 ns

Since access time of bus is overlapped with memory acess time. Pipelining is used so All 10 ns time is overlapped with 80 ns time  But for lat 16 B take 10 ns time more = 10 + 80 = 90ns.

10240 + 90 = 10330ns

--------------------------------------------------------------------------------------------------------------------------------------------------------------------

If no pipelining then  128 $\times$ (10 +80) = 11520ns

Time saved using pipeline = 11520 - 10330 = 1190ns
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