Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it to the main memory over a bus. The latency of access of both memories is 80ns each. The bus is clocked at 100 MHz, and in each bus cycle, one bus transfer is completed. The bus and both memories are 16 bytes wide each. How long does it take to complete the transfer? All possible pipelining between stages is implemented.
