0 votes 0 votes nothing is given regarding when the effective address of target instruction is available is given, what to assume? CO and Architecture made-easy-test-series co-and-architecture pipelining + – Anusha Motamarri asked Dec 1, 2016 • edited Mar 4, 2019 by akash.dinkar12 Anusha Motamarri 678 views answer comment Share Follow See all 14 Comments See all 14 14 Comments reply Show 11 previous comments Anusha Motamarri commented Dec 1, 2016 reply Follow Share @kapil yes i agree. 1 votes 1 votes Prabhanjan_1 commented Dec 1, 2016 reply Follow Share Yes i have already commented, they will give clearly when will be the target instruction available. 0 votes 0 votes Anusha Motamarri commented Dec 1, 2016 reply Follow Share yeah, in ur answer u have taken target will be available after EX stage. i was saying we cannot assume like that 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes Cycle time = Max(stage delays) + buffer delay = 12ns No of cycles are 13. So total time = 13*12ns = 156ns Prabhanjan_1 answered Dec 1, 2016 Prabhanjan_1 comment Share Follow See 1 comment See all 1 1 comment reply Anusha Motamarri commented Dec 1, 2016 reply Follow Share did u mean,as nothing is mentioned we need to assume target address is available after execution phase? 0 votes 0 votes Please log in or register to add a comment.
