MadeEasy Test Series: CO & Architecture - Cache Memory

Question

block size = 4B
no.of blocks in cache= 4
number of sets =1 
which means its fully associative,
main memory addresse 100 to 103 reside in block 26 
104 to 107- Block 27
108 to 10A -block 28 in main memory
converting given addresses to blocks 
100 104 108 104 107 108 105 102 108 103
 blocks: 26 , 27, 28, 27, 27, 28, 27, 26, 28, 26
arent there only 3 misses?
i got miss ratio = 3/10 = 0.3
please verify

Comments

But the addresses which are being generated is byte addressable right..

So for 1 word which is 32 bits wide , so we need to have 4 memory addresses for that if u consider a single word..

Actually the specifications given in question is wrong..

---

yeah,i miscalculated it. each block consists of 16Bytes ryt (as they mentioned 4 4byte words-->16bytes)
number of blocks =4,
fully associative
addresses 96 to 10B reside in same block of main memory then, only address 100 causes a miss.
when reference to 100 is made, the entire block 96 to 10B is brought to cache line. so every other reference causes a hit.
is it correct?

---

Ya so only the first access will be miss..Rest all will be hit..

So miss ratio should be 0.1 instead..

---

yea thank you :)