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We have to consider here the fact that stalls will be created due to cache miss..Now cache miss can happen either while fetching an instruction or while fetching data in case it is a load / store instruction..No other factors like branch penalty , data dependency etc are not considered for stall in this question as only mention of cache miss is there..

So 

Stalls / instruction in case of instruction fetch  = Cache miss rate * Miss penalty

                                                                    = 0.15 * 50

                                                                    = 7.5 cycles

Stalls / instruction in case of data fetch           = Fraction of Load/Store instruction * Cache Miss rate * Miss penalty

                                                                    = 0.3 * 0.15 * 50

                                                                    = 2.25 cycles

So

                                    CPIwith stall                = CPIideal + Stalls

                                                                   = 1.1 + 7.5 + 2.25

                                                                   = 10.85 cycles

So for comparision of both we find speedup ..Hence 

                                    Speed up                 =  CPIwith stall  / CPIwithout stall

                                                                   =  10.85 / 1.1

                                                                   =   9.86

Thus we can say the CPU in ideal condition (without any miss) is 9.86 times faster than the one having stalls..                 

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rahul sharma 5 asked Nov 6, 2017
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What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer