In Master Slave concept it states that Master works when clock goes from o to 1(assume +ve adge triggered),and slave works when clock goes from 1 to 0 ,so it means effective work is done only in half of the clock time and for the remaning half we have transfered data from slave the actual output?
Does this same thing apply to all +ve edge trigered circuits that they works only for half of the clock duration?
I hope question makes sense?
