edited by
445 views
0 votes
0 votes

I got C as answer.In case enable to multiplexer is 0(MUX is disabled),it should not output 0 as per my understanding as 0 represents valid data?so after I7,I6 MUX is diabled for two clock pulses as per circuit working,then how can we assume that output is 0?It should be nothing(not even 0).Please help 

edited by

1 Answer

0 votes
0 votes
according to down counter value decreses by 1 everytime and when A1 bit become 0 output will be disabled.

Related questions

0 votes
0 votes
1 answer
1
Na462 asked Jan 16, 2019
1,487 views
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be :K = 1 , Cin = 1 , B = 1K = 0 , Cin = 1 , B = 1K = 0 , Cin = 1 , B = 0 K = 1 ...
2 votes
2 votes
2 answers
3
shu asked Feb 2, 2017
550 views
Some please tell how to solve this question ?
0 votes
0 votes
1 answer
4
S Ram asked Jan 23, 2017
419 views
\can someone please help me to solve this with proper diagram?