Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How many clock cycles miss penalty reduced?
a.472.5
b.473.5
c.372.5
d.442.5
Actual Question:
CPI of 1.0 on a 5GHz machine with a 2% miss rate,
– 100ns DRAM access
– Adding a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%,
what miss penalty reduced?