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Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How many clock cycles miss penalty reduced?
a.472.5

b.473.5

c.372.5

d.442.5

 

Actual Question:

CPI of 1.0 on a 5GHz machine with a 2% miss rate,
– 100ns DRAM access
– Adding a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%,
what miss penalty reduced?
asked in CO & Architecture by Loyal (4.6k points)  
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Hey bro, I guess he may charge you if you're caught sharing his content. Don't write "Ravula tests" .
kk. from next time i will keep it in my mind
sir, I think maybe the test series team of Ravula sir have picked questions from the above link.
^Obviously. I can copy but you cannot.
Arjun Sir can u please explain it in bit detailed manner because firstly I'm not getting the question and secondly whatever is given in slide as a solution, that too I'm unable to get.
Initial miss penalty = 100ns. (Question assumes an L1 cache)

Initial avg. miss penalty per instruction = 0.02 * 100 = 2 ns.

New avg. miss penalty per instruction = 0.005 * 100 + 0.02 * 5 = 0.6 ns.

So, decrease in miss penalty = 1.4 ns = 1.4 ns * 5 GHz = 7 clock cycles.

In the question, "decrease of overall main memory miss rate to 0.5%" should be "decrease of overall main memory request rate to 0.5%"

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