1 votes 1 votes CO and Architecture co-and-architecture pipelining + – monty asked Dec 30, 2016 retagged Nov 13, 2017 by Arjun monty 329 views answer comment Share Follow See all 2 Comments See all 2 2 Comments reply monty commented Dec 30, 2016 reply Follow Share @ pC pls explain 0 votes 0 votes BASANT KUMAR commented Dec 19, 2018 reply Follow Share total 12 clock cycle by considering split phase(Assuming in half of cycle writing will be perform in wb stage and in half of cycle reading will be perform in id phase).correct me if i am wrong. 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes 1 2 3 4 5 6 7 8 9 10 11 12 13 I1 IF ID EX MA WB I2 IF ID EX MA WB I3 IF ID EX MA WB I4 IF ID EX MA WB Total clock cycles=13. Amit.kumar answered Jun 9, 2017 Amit.kumar comment Share Follow See all 0 reply Please log in or register to add a comment.