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A 4-stage pipeline has the stage delay 100, 150, 170, 180 nanoseconds respectively. Registers that are used between the stages have a delay of 2 nanoseconds each. Assuming constant clock rate, the total time taken to process 520 data items on this pipeline will be ________ μs. (Upto 2 decimal places)

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  • Minimum possible clock cycle = MAX_STAGE_DELAY + REGISTER_DELAY = 180 +2 = 182ns
  • To execute $n$ instruction is a $k$ stage pipeline with clock cycle of $T_P$ we need $(k+n-1)*T_P$ cycles.

Assuming "520 data items" as $520$ instructions $\rightarrow$

$$\large\color{maroon}{\begin{align*} \text{Total Time} &= (k+n-1)*T_P \\ &=(4+520-1)*182ns \\ &=95186ns \\ &=95.19\mu s \end{align*}}$$ 

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