Please suggest a good source for understanding cache circuitory from GATE point of view (not mapping alone). And please validate the following. If someone can wrtite a blog post regarding this it will be very helpful for everyone.
Direct Mapped Cache:
No of Comparators = 1 (width is equal to no of tag bits as in all cases)
Multiplexer is not required.
Fully Associative Cache:
No of comparators = No of cache lines (or) Cache blocks
Multiplexor is again not required.
K-set Associative Mapping
No of comparators = K (No of blocks per set)
And One K-1 Multiplexors. This is done to enable parallel checking of blocks in a set.
Thanks in advance.
