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96
votes
9
answers
31
GATE CSE 2013 | Question: 45
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$
Consider an instruction pipeline with five stages without any branch prediction:Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (...
Kriss Singh
47.5k
views
Kriss Singh
asked
Sep 5, 2014
CO and Architecture
gatecse-2013
normal
co-and-architecture
pipelining
+
–
112
votes
7
answers
32
GATE CSE 2016 Set 1 | Question: 50
Consider the following proposed solution for the critical section problem. There are $n$ processes : $P_0....P_{n-1}$. In the code, function $\text{pmax}$ ... in the critical section at any time The bounded wait condition is satisfied The progress condition is satisfied It cannot cause a deadlock
Consider the following proposed solution for the critical section problem. There are $n$ processes : $P_0....P_{n-1}$. In the code, function $\text{pmax}$ returns an inte...
Sandeep Singh
47.1k
views
Sandeep Singh
asked
Feb 12, 2016
Operating System
gatecse-2016-set1
operating-system
process-synchronization
difficult
ambiguous
+
–
14
votes
5
answers
33
How to find the complexity of T(n)=T(sqrt(n)) + 1 ?
Please tell me the complete steps how to solve this problem. $ T(n) = T ( \sqrt n )+ 1$
Please tell me the complete steps how to solve this problem.$ T(n) = T ( \sqrt n )+ 1$
Jonathan Decosta
46.9k
views
Jonathan Decosta
asked
Jun 10, 2015
Algorithms
algorithms
recurrence-relation
+
–
121
votes
15
answers
34
GATE CSE 2003 | Question: 78
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the ... virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addres...
gatecse
46.5k
views
gatecse
asked
Sep 15, 2014
Operating System
gatecse-2003
operating-system
normal
virtual-memory
+
–
5
votes
2
answers
35
How many transitive relations are there on a set with n elements if a)n=1 b) n=2 c) n=3
How many transitive relations are there on a set with n elements if a)n=1 b) n=2 c) n=3
How many transitive relations are there on a set with n elements ifa)n=1 b) n=2 c) n=3
Sanjay Sharma
46.5k
views
Sanjay Sharma
asked
Mar 7, 2017
142
votes
4
answers
36
GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
A $5$ stage pipelined CPU has the following sequence of stages:IF – instruction fetch from instruction memoryRD – Instruction decode and register readEX – Execute: ...
Kathleen
45.8k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2005
co-and-architecture
pipelining
normal
+
–
84
votes
6
answers
37
GATE CSE 2017 Set 1 | Question: 31
Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements. One eigenvalue must be in $\left [ -5,5 \right ]$ The eigenvalue ... than $5$ Which of the above statements about eigenvalues of $A$ is/are necessarily CORRECT? Both I and II I only II only Neither I nor II
Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements.One eigenvalu...
Arjun
45.2k
views
Arjun
asked
Feb 14, 2017
Linear Algebra
gatecse-2017-set1
linear-algebra
eigen-value
normal
+
–
51
votes
10
answers
38
GATE CSE 2020 | Question: 53
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $\textsf{TLB}$ lookup takes $20$ ns. Each page transfer to/from the disk ... $1$ decimal places) is ___________
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $...
Arjun
44.9k
views
Arjun
asked
Feb 12, 2020
Operating System
gatecse-2020
numerical-answers
operating-system
virtual-memory
2-marks
+
–
60
votes
9
answers
39
GATE CSE 2003 | Question: 36
How many perfect matching are there in a complete graph of $6$ vertices? $15$ $24$ $30$ $60$
How many perfect matching are there in a complete graph of $6$ vertices?$15$$24$$30$$60$
Kathleen
44.9k
views
Kathleen
asked
Sep 16, 2014
Graph Theory
gatecse-2003
graph-theory
graph-matching
normal
+
–
13
votes
3
answers
40
relation
Number of relations $S$ over set $\{0,1,2,3 \}$ such that $(x,y) \in S \Rightarrow x = y$
Number of relations $S$ over set $\{0,1,2,3 \}$ such that $(x,y) \in S \Rightarrow x = y$
Lakshman Bhaiya
44.5k
views
Lakshman Bhaiya
asked
Dec 27, 2017
Set Theory & Algebra
set-theory&algebra
relations
+
–
19
votes
8
answers
41
Minimum number of comparisons required to sort 5 elements is
The minimum number of comparisons required to sort 5 elements is - 4 5 6 7
The minimum number of comparisons required to sort 5 elements is -4567
piyushkr
43.4k
views
piyushkr
asked
Dec 30, 2015
Algorithms
algorithms
sorting
+
–
39
votes
5
answers
42
GATE CSE 2009 | Question: 37,ISRO-DEC2017-55
What is the maximum height of any AVL-tree with $7$ nodes? Assume that the height of a tree with a single node is $0$. $2$ $3$ $4$ $5$
What is the maximum height of any AVL-tree with $7$ nodes? Assume that the height of a tree with a single node is $0$.$2$$3$$4$$5$
Kathleen
43.3k
views
Kathleen
asked
Sep 22, 2014
DS
gatecse-2009
data-structures
binary-search-tree
normal
isrodec2017
avl-tree
+
–
22
votes
1
answer
43
gate rank prediction
Hi i just want to ask if i am scoring 40 to 45% marks in made easy FLT s and my rank is near about 200 -250 where 1000 students have appeared what could be my gate rank as per previous year student experiences? a silly q though but i wnt to know!
Hi i just want to ask if i am scoring 40 to 45% marks in made easy FLT s and my rank is near about 200 -250 where 1000 students have appeared what could be my gate rank a...
Aboveallplayer
43.2k
views
Aboveallplayer
asked
Jan 17, 2016
70
votes
8
answers
44
GATE CSE 2005 | Question: 73
In a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is $24$ bytes and each packet contains a header of $3$ bytes, then the optimum packet size is: $4$ $6$ $7$ $9$
In a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is $24$ bytes and each...
Kathleen
42.1k
views
Kathleen
asked
Sep 22, 2014
Computer Networks
gatecse-2005
computer-networks
network-switching
normal
+
–
35
votes
2
answers
45
GATE CSE 2005 | Question: 22, ISRO2015-36
Increasing the RAM of a computer typically improves performance because: Virtual Memory increases Larger RAMs are faster Fewer page faults occur Fewer segmentation faults occur
Increasing the RAM of a computer typically improves performance because:Virtual Memory increasesLarger RAMs are fasterFewer page faults occurFewer segmentation faults occ...
Kathleen
41.7k
views
Kathleen
asked
Sep 22, 2014
Operating System
gatecse-2005
operating-system
page-replacement
easy
isro2015
+
–
100
votes
21
answers
46
GATE CSE 2016 Set 1 | Question: 54
For a host machine that uses the token bucket algorithm for congestion control, the token bucket has a capacity of $1$ $\text{megabyte}$ and the maximum output rate is $20$ $\text{megabytes}$ per $\text{second}$. Tokens arrive at a rate to ... to send $12$ $\text{megabytes}$ of data. The minimum time required to transmit the data is _____________ $\text{seconds}$.
For a host machine that uses the token bucket algorithm for congestion control, the token bucket has a capacity of $1$ $\text{megabyte}$ and the maximum output rate is $2...
Sandeep Singh
41.7k
views
Sandeep Singh
asked
Feb 12, 2016
Computer Networks
gatecse-2016-set1
computer-networks
token-bucket
normal
numerical-answers
+
–
80
votes
8
answers
47
GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...
go_editor
40.9k
views
go_editor
asked
Sep 30, 2014
CO and Architecture
gatecse-2010
co-and-architecture
cache-memory
normal
barc2017
+
–
70
votes
5
answers
48
GATE CSE 2015 Set 3 | Question: 51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$.$$\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline...
go_editor
40.7k
views
go_editor
asked
Feb 16, 2015
CO and Architecture
gatecse-2015-set3
co-and-architecture
pipelining
difficult
numerical-answers
+
–
47
votes
8
answers
49
GATE CSE 2006 | Question: 46
Station $A$ needs to send a message consisting of $9$ packets to Station $B$ using a sliding window (window size $3$) and go-back-$n$ error control strategy. All packets are ready and immediately available for transmission. If every $5$th packet that $A$ ... what is the number of packets that $A$ will transmit for sending the message to $B$? $12$ $14$ $16$ $18$
Station $A$ needs to send a message consisting of $9$ packets to Station $B$ using a sliding window (window size $3$) and go-back-$n$ error control strategy. All packets ...
Rucha Shelke
40.7k
views
Rucha Shelke
asked
Sep 26, 2014
Computer Networks
gatecse-2006
computer-networks
sliding-window
normal
+
–
3
votes
1
answer
50
Given the data word 101001111 and the divisor 10111, show the generation of the CRC code word at the sender side
Please give me a solution to this with working
rahuldb
40.5k
views
rahuldb
asked
Oct 21, 2016
Computer Networks
computer-networks
+
–
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