Search results for 2017

150 votes

18 answers

1

GATE CSE 2017 Set 2 | Question: 44
Two transactions $T_1$ and $T_2$ are given as $T_1:r_1(X)w_1(X)r_1(Y)w_1(Y)$ $T_2:r_2(Y)w_2(Y)r_2(Z)w_2(Z)$ where $r_i(V)$ denotes a $\textit{read}$ operation by transaction $T_i$ on a variable $V$ and $w_i(V)$ denotes a ... by transaction $T_i$ on a variable $V$. The total number of conflict serializable schedules that can be formed by $T_1$ and $T_2$ is ______

Two transactions $T_1$ and $T_2$ are given as$T_1:r_1(X)w_1(X)r_1(Y)w_1(Y)$$T_2:r_2(Y)w_2(Y)r_2(Z)w_2(Z)$where $r_i(V)$ denotes a $\textit{read}$ operation by transaction...

72.7k views

Madhav asked Feb 14, 2017

88 votes

6 answers

2

GATE CSE 2017 Set 1 | Question: 31
Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements. One eigenvalue must be in $\left [ -5,5 \right ]$ The eigenvalue ... than $5$ Which of the above statements about eigenvalues of $A$ is/are necessarily CORRECT? Both I and II I only II only Neither I nor II

Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements.One eigenvalu...

49.6k views

Arjun asked Feb 14, 2017

87 votes

7 answers

3

GATE CSE 2017 Set 1 | Question: 13
Consider the following C code: #include<stdio.h> int *assignval (int *x, int val) { *x = val; return x; } void main () { int *x = malloc(sizeof(int)); if (NULL == x) return; x = assignval (x,0); ... and not as shown. compiles successfully but execution may result in dangling pointer. compiles successfully but execution may result in memory leak.

Consider the following C code:#include<stdio.h int *assignval (int *x, int val) { *x = val; return x; } void main () { int *x = malloc(sizeof(int)); if (NULL == x) return...

35.4k views

Arjun asked Feb 14, 2017

91 votes

9 answers

4

GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory ... $10$ times. The number of conflict misses experienced by the cache is _________ .

Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur d...

38.6k views

Arjun asked Feb 14, 2017

78 votes

5 answers

5

GATE CSE 2017 Set 2 | Question: 45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: ... and $40\%$ are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________

The read access times and the hit ratios for different caches in a memory hierarchy are as given below:$$\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access ...

30.0k views

Madhav asked Feb 14, 2017

70 votes

13 answers

6

GATE CSE 2017 Set 2 | Question: 55
Consider the following C program. #include<stdio.h> #include<string.h> int main() { char* c="GATECSIT2017"; char* p=c; printf("%d", (int)strlen(c+2[p]-6[p]-1)); return 0; } The output of the program is _______

Consider the following C program.#include<stdio.h #include<string.h int main() { char* c="GATECSIT2017"; char* p=c; printf("%d", (int)strlen(c+2[p]-6[p]-1)); return 0; }T...

27.9k views

Madhav asked Feb 14, 2017

77 votes

12 answers

7

GATE CSE 2017 Set 2 | Question: 39
Let $\delta$ denote the transition function and $\widehat{\delta}$ denote the extended transition function of the $\epsilon$ ... $\emptyset$ $\{q_0, q_1, q_3\}$ $\{q_0, q_1, q_2\}$ $\{q_0, q_2, q_3 \}$

Let $\delta$ denote the transition function and $\widehat{\delta}$ denote the extended transition function of the $\epsilon$-NFA whose transition table is given below:$$\...

28.4k views

Arjun asked Feb 14, 2017

122 votes

7 answers

8

GATE CSE 2017 Set 1 | Question: 27
A multithreaded program $P$ executes with $x$ number of threads and uses $y$ number of locks for ensuring mutual exclusion while operating on shared memory locations. All locks in the program are non-reentrant, i.e., if a thread holds a lock $l$, then it cannot re-acquire lock $l$ without releasing ... $x = 1, y = 2$ $x = 2, y = 1$ $x = 2, y = 2$ $x = 1, y = 1$

A multithreaded program $P$ executes with $x$ number of threads and uses $y$ number of locks for ensuring mutual exclusion while operating on shared memory locations. All...

33.3k views

Arjun asked Feb 14, 2017

54 votes

15 answers

9

GATE CSE 2017 Set 1 | Question: 22
Consider the language $L$ given by the regular expression $(a+b)^{*} b (a+b)$ over the alphabet $\{a,b\}$. The smallest number of states needed in a deterministic finite-state automaton (DFA) accepting $L$ is ___________ .

Consider the language $L$ given by the regular expression $(a+b)^{*} b (a+b)$ over the alphabet $\{a,b\}$. The smallest number of states needed in a deterministic finite-...

29.3k views

Arjun asked Feb 14, 2017

35 votes

11 answers

10

GATE CSE 2017 Set 2 | Question: 13
A circular queue has been implemented using a singly linked list where each node consists of a value and a single pointer pointing to the next node. We maintain exactly two external pointers FRONT and REAR pointing to the front node and the rear node of the queue, respectively ... to the front node. (I) only. (II) only. Both (I) and (II). Neither (I) nor (II).

A circular queue has been implemented using a singly linked list where each node consists of a value and a single pointer pointing to the next node. We maintain exactly t...

27.6k views

Madhav asked Feb 14, 2017

67 votes

6 answers

11

GATE CSE 2017 Set 2 | Question: 29
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average ... respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$

In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory i...

28.6k views

Arjun asked Feb 14, 2017

83 votes

4 answers

12

GATE CSE 2017 Set 1 | Question: 42
In a database system, unique timestamps are assigned to each transaction using Lamport's logical clock. Let $TS(T_{1})$ and $TS(T_{2})$ be the timestamps of transactions $T_{1}$ and $T_{2}$ ... -free. The database system is starvation-free, but not deadlock-free. The database system is neither deadlock-free nor starvation-free.

In a database system, unique timestamps are assigned to each transaction using Lamport's logical clock. Let $TS(T_{1})$ and $TS(T_{2})$ be the timestamps of transactions ...

27.0k views

Arjun asked Feb 14, 2017

56 votes

10 answers

13

GATE CSE 2017 Set 1 | Question: 48
Let $A$ be an array of $31$ numbers consisting of a sequence of $0$'s followed by a sequence of $1$'s. The problem is to find the smallest index $i$ such that $A\left [i \right ]$ is $1$ by probing the minimum number of locations in $A$. The worst case number of probes performed by an optimal algorithm is ____________.

Let $A$ be an array of $31$ numbers consisting of a sequence of $0$'s followed by a sequence of $1$'s. The problem is to find the smallest index $i$ such that $A\left [i ...

21.8k views

Arjun asked Feb 14, 2017

58 votes

7 answers

14

GATE CSE 2017 Set 1 | Question: 45
The values of parameters for the Stop-and-Wait ARQ protocol are as given below: Bit rate of the transmission channel $= 1$ Mbps. Propagation delay from sender to receiver $= 0.75$ ms. Time to process a frame $= 0.25$ ms. Number ... (expressed in percentage) of the Stop-and-Wait ARQ protocol for the above parameters is _____________ (correct to $2$ decimal places).

The values of parameters for the Stop-and-Wait ARQ protocol are as given below:Bit rate of the transmission channel $= 1$ Mbps.Propagation delay from sender to receiver $...

33.0k views

Arjun asked Feb 14, 2017

57 votes

11 answers

15

GATE CSE 2017 Set 1 | Question: 43
Consider the following grammar: stmt $\rightarrow$ if expr then expr else expr; stmt | $Ò$ expr $\rightarrow$ term relop term | term term $\rightarrow$ id | number id $\rightarrow$ a | b | c number $\rightarrow [0-9]$ where relop is a relational ... program if $e_1$ then $e_2$ else $e_3$ has $2$ control flow paths. $e_1 \rightarrow e_2$ and $e_1 \rightarrow e_3$.

Consider the following grammar:stmt $\rightarrow$ if expr then expr else expr; stmt | $Ò$expr $\rightarrow$ term relop term | termterm $\rightarrow$ id | numberid $\righ...

20.4k views

Arjun asked Feb 14, 2017

67 votes

9 answers

16

GATE CSE 2017 Set 1 | Question: 3
Let $c_{1}.....c_{n}$ be scalars, not all zero, such that $\sum_{i=1}^{n}c_{i}a_{i}$ = 0 where $a_{i}$ are column vectors in $R^{n}$. Consider the set of linear equations $Ax = b$ ... has a unique solution at $x=J_{n}$ where $J_{n}$ denotes a $n$-dimensional vector of all 1. no solution infinitely many solutions finitely many solutions

Let $c_{1}.....c_{n}$ be scalars, not all zero, such that $\sum_{i=1}^{n}c_{i}a_{i}$ = 0 where $a_{i}$ are column vectors in $R^{n}$.Consider the set of linear equations$...

20.3k views

Arjun asked Feb 14, 2017

73 votes

8 answers

17

GATE CSE 2017 Set 1 | Question: 02
Consider the first-order logic sentence $F:\forall x(\exists yR(x,y))$. Assuming non-empty logical domains, which of the sentences below are implied by $F$? $\exists y(\exists xR(x,y))$ $\exists y(\forall xR(x,y))$ $\forall y(\exists xR(x,y))$ $¬\exists x(\forall y¬R(x,y))$ IV only I and IV only II only II and III only

Consider the first-order logic sentence $F:\forall x(\exists yR(x,y))$. Assuming non-empty logical domains, which of the sentences below are implied by $F$?$\exists y(\ex...

17.3k views

khushtak asked Feb 14, 2017

103 votes

9 answers

18

GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rat...

24.3k views

Arjun asked Feb 14, 2017

56 votes

3 answers

19

GATE CSE 2017 Set 1 | Question: 52
Consider the expression $(a-1) * (((b+c)/3)+d)$. Let $X$ be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which only load and store ... memory operands and arithmetic instructions can have only register or immediate operands. The value of $X$ is _____________ .

Consider the expression $(a-1) * (((b+c)/3)+d)$. Let $X$ be the minimum number of registers required by an optimal code generation (without any register spill) algorithm ...

19.3k views

Arjun asked Feb 14, 2017

104 votes

7 answers

20

GATE CSE 2017 Set 1 | Question: 36
Consider the C functions foo and bar given below: int foo(int val) { int x=0; while(val > 0) { x = x + foo(val--); } return val; } int bar(int val) { int x = 0; while(val > 0) { x ... in: Return of $6$ and $6$ respectively. Infinite loop and abnormal termination respectively. Abnormal termination and infinite loop respectively. Both terminating abnormally.

Consider the C functions foo and bar given below:int foo(int val) { int x=0; while(val 0) { x = x + foo(val ); } return val; }int bar(int val) { int x = 0; while(val 0)...

25.3k views

Arjun asked Feb 14, 2017

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