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Search results for addressing-modes
97
votes
8
answers
1
GATE CSE 2005 | Question: 65
Consider a three word machine instruction $\text{ADD} A[R_0], @B$ The first operand (destination) $ A[R_0] $ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) $ @B $ uses indirect addressing mode. $A$ and $B$ ... (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$
Consider a three word machine instruction$\text{ADD} A[R_0], @B$The first operand (destination) $“A[R_0]”$ uses indexed addressing mode with $R_0$ as the index regist...
Kathleen
33.9k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2005
co-and-architecture
addressing-modes
normal
+
–
45
votes
6
answers
2
GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode
The most relevant addressing mode to write position-independent codes is:Direct modeIndirect modeRelative modeIndexed mode
makhdoom ghaya
15.0k
views
makhdoom ghaya
asked
Nov 8, 2016
CO and Architecture
gate1987
co-and-architecture
addressing-modes
easy
+
–
54
votes
3
answers
3
GATE CSE 1999 | Question: 2.23
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers Arrays Records Recursive procedures with local variable
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this proces...
Kathleen
15.4k
views
Kathleen
asked
Sep 23, 2014
CO and Architecture
gate1999
co-and-architecture
addressing-modes
normal
multiple-selects
+
–
32
votes
5
answers
4
GATE CSE 2002 | Question: 1.24
In the absolute addressing mode: the operand is inside the instruction the address of the operand in inside the instruction the register containing the address of the operand is specified inside the instruction the location of the operand is implicit
In the absolute addressing mode:the operand is inside the instructionthe address of the operand in inside the instructionthe register containing the address of the operan...
Kathleen
13.7k
views
Kathleen
asked
Sep 15, 2014
CO and Architecture
gatecse-2002
co-and-architecture
addressing-modes
easy
+
–
35
votes
6
answers
5
GATE CSE 1996 | Question: 1.16, ISRO2016-42
Relative mode of addressing is most relevant to writing: Co – routines Position – independent code Shareable code Interrupt Handlers
Relative mode of addressing is most relevant to writing:Co – routinesPosition – independent codeShareable codeInterrupt Handlers
Kathleen
12.5k
views
Kathleen
asked
Oct 9, 2014
CO and Architecture
gate1996
co-and-architecture
addressing-modes
easy
isro2016
+
–
58
votes
4
answers
6
GATE CSE 2008 | Question: 33, ISRO2009-80
Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed I only II only III only II and III only
Which of the following is/are true of the auto-increment addressing mode?It is useful in creating self-relocating codeIf it is included in an Instruction Set Architecture...
Kathleen
18.3k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gatecse-2008
addressing-modes
co-and-architecture
normal
isro2009
+
–
1
votes
3
answers
7
MADE EASY TEST SERIES 2024 #COA
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ADD operation with Address 1 used as Source1 and Destination, Address2 used ... operation consumes 4 cycles. Memory reference consumes 6 cycles. Time required to complete the instruction is in (ns).
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ...
Shaikh727
369
views
Shaikh727
asked
Jan 24
CO and Architecture
co-and-architecture
made-easy-test-series
addressing-modes
+
–
1
votes
4
answers
8
Made Easy Test Series 2024
( Numerical Answer Type Questionm )
( Numerical Answer Type Questionm )
Ray Tomlinson
751
views
Ray Tomlinson
asked
Sep 6, 2023
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
+
–
48
votes
5
answers
9
GATE CSE 2011 | Question: 21
Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ ... mode implemented by this instruction for the operand in memory? Immediate addressing Register addressing Register Indirect Scaled Addressing Base Indexed Addressing
Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a ...
go_editor
17.4k
views
go_editor
asked
Sep 29, 2014
CO and Architecture
gatecse-2011
co-and-architecture
addressing-modes
easy
+
–
0
votes
1
answer
10
Addressing Modes
lea
290
views
lea
asked
Jun 12, 2023
CO and Architecture
co-and-architecture
addressing-modes
+
–
29
votes
3
answers
11
GATE CSE 1989 | Question: 2-ii
Match the pairs in the following questions: ...
Match the pairs in the following questions:$$\begin{array}{ll|ll}\hline \text{(A)} & \text{Base addressing} & \text{(p)} & \text{Reentranecy} \\\hline \text{(B)} & \text...
makhdoom ghaya
5.8k
views
makhdoom ghaya
asked
Nov 27, 2016
CO and Architecture
gate1989
match-the-following
co-and-architecture
addressing-modes
easy
+
–
0
votes
2
answers
12
Addressing mode
lea
305
views
lea
asked
Jun 12, 2023
CO and Architecture
computer-architecture
addressing-modes
+
–
0
votes
1
answer
13
Addressing mode
lea
366
views
lea
asked
Jun 12, 2023
Operating System
operating-system
addressing-modes
+
–
40
votes
4
answers
14
GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing
Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relat...
Kathleen
10.9k
views
Kathleen
asked
Sep 25, 2014
CO and Architecture
gate1998
co-and-architecture
addressing-modes
easy
+
–
49
votes
3
answers
15
GATE CSE 2017 Set 1 | Question: 11
Consider the $C$ struct defined below: struct data { int marks [100]; char grade; int cnumber; }; struct data student; The base address of student is available in register $R1$. The field student.grade can be accessed efficiently using: Post-increment ... mode, $X(R1)$, where $X$ is an offset represented in $2's$ complement $16\text{-bit}$ representation
Consider the $C$ struct defined below:struct data { int marks [100]; char grade; int cnumber; }; struct data student;The base address of student is available in register...
Arjun
14.4k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
addressing-modes
+
–
6
votes
4
answers
16
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
The immediate addressing mode can be used forLoading internal registers with initial valuesPerform arithmetic or logical operation on data contained in instructionsWhich ...
Satbir
3.9k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
normal
addressing-modes
+
–
31
votes
3
answers
17
GATE CSE 1993 | Question: 10
The instruction format of a CPU is: $\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an addressing mode. In particular, $\text{Mode}=2$ specifies that ... address of the operand? Assuming that is a non-jump instruction, what are the contents of PC after the execution of this instruction?
The instruction format of a CPU is:$\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an add...
Kathleen
7.0k
views
Kathleen
asked
Sep 29, 2014
CO and Architecture
gate1993
co-and-architecture
addressing-modes
normal
descriptive
+
–
56
votes
3
answers
18
GATE IT 2006 | Question: 39, ISRO2009-42
Which of the following statements about relative addressing mode is FALSE? It enables reduced instruction size It allows indexing of array element with same instruction It enables easy relocation of data It enables faster address calculation than absolute addressing
Which of the following statements about relative addressing mode is FALSE?It enables reduced instruction sizeIt allows indexing of array element with same instructionIt e...
Ishrat Jahan
14.8k
views
Ishrat Jahan
asked
Oct 31, 2014
CO and Architecture
gateit-2006
co-and-architecture
addressing-modes
normal
isro2009
+
–
0
votes
0
answers
19
Relative Addressing Mode
Consider 3-word long jump instruction designed with PC-relative addressing mode, stored in the memory with a starting address of (2000)$_{10}$. Address field of an instruction contains (4000)$_{10}.$ Which of the following statements are true in the instruction ... where operand is stored, then how we can we assign it to PC? PC should be 2003 at the end of execution right?
Consider 3-word long jump instruction designed with PC-relative addressing mode, stored in the memory with a starting address of (2000)$_{10}$. Address field of an instru...
Chaitanya Kale
603
views
Chaitanya Kale
asked
Feb 13, 2023
CO and Architecture
addressing-modes
co-and-architecture
made-easy-test-series
+
–
0
votes
1
answer
20
consider 16tb disk that uses 4kb block and free list method. how many block address can be stored in a block
Shubham Kathiriya
561
views
Shubham Kathiriya
asked
Jan 26, 2023
Operating System
operating-system
addressing-modes
+
–
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